Hi-speed digitally clocked systems are typically very noisy with regard to electromagnetic interference (EMI) emissions, unless some special care is taken at the design stage of equipment incorporating such clocked systems. One reliable and low-cost method for reducing EMI emissions is to use a spread spectrum clock such as is disclosed in U.S. Pat. Nos. 5,488,627 and 5,631,920. These patents disclose circuits in which the spread spectrum frequencies are varied by the use of programmable counters and by data stored in a memory circuit. These U.S. Pat. Nos. 5,488,627 and 5,631,920 are commonly-assigned, and are incorporated herein by reference in their entireties.
In a U.S. patent application, Ser. No. 09/169,110 (filed Oct. 8, 1998), a digital spread spectrum clock circuit is disclosed in which the clock is made variable by using Random Access Memory and a multiplexer to receive initiation data before the clock circuit is ready to run normally. This application is titled "Variable Spread Spectrum Clock," and is commonly-assigned to Lexmark International, Inc., and is incorporated herein by reference in its entirety.
While such prior spread spectrum clocks have often been disclosed or constructed using phase locked loop circuits, other types of frequency synthesizer circuits can be made into a spread spectrum clock, including digital locked loop circuits and delay locked loop circuits. One example of a digital locked loop circuit is disclosed in U.S. Pat. No. 5,079,519, and one example of a delay locked loop circuit is disclosed in U.S. Pat. No. 5,771,264.
The spread spectrum clock generator (SSCG) designs previously available have a design sensitivity to the voltage controlled oscillator gain, charge pump current, and passive component values (in connection with phase locked loop circuits). It would be an improvement to correct, automatically or under control of a computer program, the sensitive parameters by modifying the SSCG circuit.